Verification Engineer Design Jobs

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Today

Graphics Design Verification Engineer

Apple Austin, TX

Austin, TX

Today

Full time Design Verification Hardware Engineer Hardware Verification

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Job Description

The Graphics Design Verification Engineer supports pre-silicon verification for low power embedded graphics cores within Apple SoC/GPU design efforts. This role focuses on GPU design verification, building SystemVerilog and UVM-based test infrastructure, executing verification plans, and diagnosing simulation and silicon issues.

Responsibilities

Lead top-level verification for logic blocks in graphics processing unit (GPU) designs.
Write, execute, and track verification work against defined test plans.
Develop test bench components using SystemVerilog and UVM, including checkers and monitors.
Create top-level tests to validate chip-level features.
Enable and maintain regressions.
Write and maintain test benches and BFMs (bus functional models).
Generate stimulus and implement and analyze coverage.
Debug simulation and silicon failures related to GPU behavior.
Partner with design and micro-architecture teams to understand functional goals of the design.
Collaborate with multi-functional teams to coordinate verification activities across DV scopes.
Develop scripts for software engineering flows.

Required Qualifications

BS plus 3 years of relevant experience.
Background in CPU or GPU architectures.
Experience working with Verilog or other HDLs.
Experience with verification languages such as SystemVerilog, UVM, or OVM.
Experience using HDL simulators and waveform viewers including IES, VCS, DVE, and Verdi.

Preferred Qualifications

Experience working with GPU architectures.
Understanding of constrained random verification, functional/code coverage, and assertion methodology.
Experience developing UVM test bench components including checkers and monitors.
Familiarity with Perl, Shell scripting, Makefiles, and TCL.
Prior exposure to code repositories such as Perforce.
Ability to work well on a team collaborating with other teams.

Technology Stack

System Verilog
UVM
OVM
Verilog
IES, VCS, DVE, Verdi
Perl
Shell scripting, Makefiles, TCL
Perforce

Role Details

Location: Austin, TX (onsite)
Minimum experience: 3 years
Education: BS

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